1. Field of the Invention
This invention relates to a method and computer program for generation of a capacitance value rule table for extraction of the wiring capacitance of an LSI device, and in particular to a method and computer program capable of rapid generation of a capacitance value rule table to be referenced when extracting the wiring capacitance of multilayer wiring having a complex structure of dielectric constant.
2. Description of the Related Art
LSI device design processes are normally performed with CAD executed by a computer. LSI device design processes include a logic design process to design the logic circuitry connecting logic gates; a layout design process to lay out the logic circuitry on an actual chip; a process to extract RLC values (resistances, inductances, capacitances) of the layout interconnects from the layout data, and to determine delay times for each signal path from the extracted RLC values and from cell and macro AC characteristics; a timing verification (logic verification) process to check whether, using these delay times, the logic circuit operates normally; and a physical verification process to check, based on the layout data, whether design rules are satisfied. Through layout design, the layout data including wiring pattern data for each layer on the chip is created, and based on this layout data the RLC values for interconnects are extracted. An RLC extraction process, delay time calculation process, and logic simulation process are generally provided by a single program module.
In the above RLC extraction process, the resistances R, capacitances C and inductances L of interconnects are extracted, referencing the RLC rule table, according to the widths of wires contained in the layout data, the distances between neighboring wires, overlap areas and similar. That is, a rule table having RLC values for interconnects determined according to wire distances and other parameters is generated in advance from LSI process rules which specify the multilayer wiring structure, and when RLC values are extracted for interconnects in the actual layout, the parameters of actual interconnects are matched with the parameters of the RLC rule table, and RLC values corresponding to matching parameters are extracted from the rule table. Such an RLC value extraction method has for example been disclosed in Japanese Patent Laid-open No. 2002-368088 (FIG. 1 and FIG. 12, for example).
As another RLC extraction method, it has been proposed that capacitance values be computed in an adjacent wiring structure of actual interconnects based on layout data, as for example in Japanese Patent Laid-open No. 2002-299456.